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Posted by mmaker@my-deja.com on 04/13/07 15:30
On Apr 13, 4:07 pm, "nappy" <s...@spam.com> wrote:
> <mma...@my-deja.com> wrote in message
> > But if the CPU is having to access RAM, it's already screwed because
> > the latency of memory accesses is large no matter how fast they run.
> WHAT?
Is it really that difficult to understand? If your data isn't in the
cache, you have to wait for the memory access to get out onto the bus
and talk to the RAM... saving a few clock cycles with faster RAM
doesn't make much difference to an operation that takes tens of clock
cycles anyway.
That's why AMD got a speedup by putting the memory controller on the
CPU, and why Intel keep adding larger and larger caches.
Mark
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